The present invention relates to CCD devices. The present invention particularly relates to area CCD imagers having multiplexed serial output registers.
A problem in CCDs with relatively large pixel dimensions is that, in any portion of a single CCD element wherein the potential profile for carriers is flat, carrier transport will be diffusion-dominated. This means that a tradeoff between charge transfer efficiency and clock rate becomes necessary, at least if reasonably high clock rates are desired. This tradeoff is extremely undesirable, since the application desired (for example NTSC compatibility) will often strictly dictate the clock rates which must be used, and any degradation whatsoever in charge transfer efficiency is extremely undesirable.
To avoid this tradeoff, the prior art teaches modification of the CCD pixel structure to create potential gradients within a single pixel. That is, for example, instead of a single clocked well implant, multiple clocked well implants might be used. That is, under the clocked electrode, there will be not merely two potential levels (barrier and well) but three or more (for example, upper barrier, lower barrier, and well). That is, without modifying the highest and lowest potential levels within a single phase of the CCD, intermediate potential levels may be introduced, to reduce the width of regions of flat potential, so that more of the carrier transport distance is dominated by potential gradient rather than by carrier diffusion statistics.
However, the prior art method of using multiple implants to do this (one implant for each additional potential level) is very expensive; anything which introduces an additional mask level into a process is undesirable.
The present invention teaches an alternative way to achieve modification of the potential profile to assist carrier transport within large CCD elements; the mask geometry of the patterned implants is modified. For example, in the context of a virtual phase CCD process, the patterned virtual well implant can be modified so that it includes small wedge-shaped protrusions, where small portions of the virtual well implant extend out into the virtual barrier region. That is, the boundary between the virtual well and the virtual barrier does not extend straight across the channel width, but is interrupted by these wedge-shaped protrusions. Two-dimensional effects at the boundaries of these protrusions cause a potential modification. That is, the relatively narrow protrusions themselves have a higher potential than the virtual well, due to the two dimensional effects, and this itself creates an additional intermediate potential level, without any additional patterning. This itself is a first teaching of the invention, and provides numerous key advantages.
A further teaching of the invention is that these relatively narrow protrusions should be tapered, so that not only is an intermediate level of potential provided, but this level of potential is itself subject to a potential gradient. That is, the present invention not only provides a third (intermediate) potential level between the flat potentials of the virtual barrier and virtual well, but this intermediate potential level is itself graduated, which further reduces the transport distance over which carrier transport is diffusion-dominated.
Such enhancements to carrier transport may be advantageous where very large pixels are used in the imaging area, e.g. for long integration time (low light level) or rad-hard devices, or in the memory array area of a device using on-chip integration of multiple imaged charge packets into a single memory charge packet; but the primary need for this technology arises in serial transfer registers, particularly where the serial transfer registers are multiplexed onto more than one column of a CCD array and are operated generally at high clocking frequencies
In color imagers generally, it is desirable to segregate the column outputs into more than one serial register and output amplifier. Separation of the color channels also assists in off-chip processing. For example, an area CCD imager with RBG color filter striping overlaid on the imager could be multiplexed onto three serial output registers, so that the CCD pixel pitch of each of the serial output registers would have to be three times the horizontal column separation of the CCD array. For even a reasonably small array, e.g., an eleven millimeter diagonal 488 by 780 array, this can require very large pixel sizes in the serial output registers, e.g., 20 microns or more pixel pitch. This pitch is large enough that diffusion-dominated transport can lead to degraded CTE at the clocking rates required for NTSC compatibility.
Thus it is an advantage of the present invention that high charge transfer efficiency can be achieved in large-pitch CCD pixel structures without requiring additional masking steps.
It is a further advantage of the present invention that high charge transfer efficiency at high clocking rates can be achieved in area CCD imaging arrays having column outputs multiplexed onto to more than one serial output register.
According to the present invention there is provided: A CCD structure comprising: a plurality of pixels connected in series along a CCD channel, each said pixel comprising a plurality of adjacent phases, each said phase comprising A well region, a barrier region, and at least one intermediate potential region between said well region and said barrier region, said well region adjoining a barrier region of a different one of said phases and said barrier region adjoining a well region of a different one of said phases; wherein at least some of said pixels comprise, in at least one phase thereof, a boundary of at least one of said intermediate potential regions which is not straight, but includes protrusions directed approximately along said channel, said protrusions being substantially narrower than the width of said channel.